I. Field of the Invention
This invention is related to protection devices/circuits and, more particularly, to protection circuits for protecting an electronic circuit, such as an integrated circuit, from an electrostatic discharge (ESD) event.
II. Description of Related Art
ESD protection devices and/or circuits are important to preventing the failure of many electronic components. Integrated circuits (ICs) in particular need to be protected against ESD pulses that occur during manufacturing operations associated with such components. Various techniques and approaches have been employed to protect electronic circuits, particularly ICs from such ESD pulses.
One type of protection that is employed for ESD protection is the use of power supply protection circuits, which are typically included on-chip (e.g., on the IC itself) to keep ESD pulses from damaging the IC's during physical manipulation of the ICs. Many of such protection circuits operate based on a ‘snap-back’ behavior of the protection device/circuit. As is known, snap-back occurs in such devices/circuits once a given voltage level is exceeded. An additional aspect of power supply protection devices/circuits is that they are latch-up safe (e.g., so that they are not triggered and then remain on for an extended duration during normal operation of the circuit they are protecting). Latch-up is a known phenomenon that may occur in parasitic bipolar devices that are inherently created in the physical layout of ICs. Thus, when power supply protection devices/circuits with a snap-back behavior are used, the holding voltage of those protection devices/circuits must be higher than the supply voltage (VDD) in order for such protection devices/circuits to be “latch-up safe.”
In harsh operating environments, such as automotive environments, ESD power supply protection devices/circuits (e.g., such as those using snap-back devices) may trigger during normal operation due to over voltage conditions that occur due to the harsh operating environment. In this situation, if the power supply protection device/circuit clamps the voltage to a value at, or below the operating voltage, the protection circuit would “latch-up” and destroy the IC due to a large DC supply current flowing directly from the power supply terminal to the reference voltage terminal (e.g., electrical ground) through the ESD protection circuit. Therefore, a holding voltage that is sufficiently higher than the nominal supply voltage to prevent such latch-up is desirable for ESD power supply protection devices/circuits operating in such harsh environments.
In the automotive industry, 42V battery supply voltages are becoming common. Thus, for ICs or electronic circuits employed in this environment, a holding voltage of at least 50V for ESD power supply protection circuits using snap-back devices is desirable. This high holding voltage, along with the requirement of many automotive manufacturers for high ESD current dissipation capability (e.g., the ability to sustain a human body model ESD pulse of >4 kV), power supply protection devices/circuits that have a power dissipation capability of 150 W or more in a 100 ns time period are necessary.
One type of protection circuit that has been implemented in such environments is ‘active clamp’ circuits. Such active clamps, which are essentially over-sized bipolar or double-diffused metal-oxide-semiconductor (DMOS) transistors, are capable of safely operating under very high ESD currents. Also, because they do not operate based on snap-back behavior, they are not particularly susceptible to latch-up. However, such devices, when implemented in an integrated-circuit (IC) consume a relatively large silicon area and, therefore, are expensive to employ. Therefore, ESD protection circuits that satisfy harsh environment performance criteria (e.g., the automotive criteria discussed above) that may be implemented in a cost effective way (e.g., with relatively little silicon area) are desirable.